The present invention relates generally to three-dimensional memory devices and related programming methods.
The development of semiconductor devices, such as semiconductor memory devices, is one characterized by a constant quest for enhanced functionality, better operating speeds, and increased integration density. One approach taken to the fabrication of semiconductor memory devices with increased integration density (e.g., a higher number of memory cells per unit area of a substrate surface) involves the vertical stacking of multiple substrates to form 3-dimensional memory devices. Conventional 3-dimensional memory devices are disclosed, for example, in U.S. Pat. No. 5,835,396 issued on Nov. 10, 1998 and titled “Three-Dimensional Read-Only Memory”; U.S. Pat. No. 6,034,882 issued on Mar. 7, 2000 and titled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication”; and U.S. Pat. No. 7,002,825 issued on Feb. 21, 2006 and titled “Word Line Arrangement Having Segmented Word Line”. The collective subject matter of these documents is hereby incorporated by reference.
Such 3-dimensional memory devices generally include a memory cell array formed on each one of a plurality of material layers. Each material layer may be formed, for example, by a silicon substrate or a silicon-on-insulator (SOI) structure. One or more of the material layers may include a layer grown using an epitaxial fabrication process.